GPU GDDR6/6X PHY and Controllers

Graphics Double Data Rate (GDDR) is a modern type of Synchronous Graphics Random-Access Memory (SGRAM) with a high bandwidth DDR interface designed for use in graphics cards, game consoles, and high-performance computing. GDDR6/6X are currently the highest-bandwidth GDDR memory solutions, capable of supporting increased per-pin bandwidth (up to 21Gbps for GDDR6X, 16Gbps for GDDR6), lower operating voltages (1.35V), higher performance and lower power consumption compared to GDDR5/GDDR5X.

The Innosilicon GDDR6 PHY is the world’s first silicon proven commercial GDDR6 IP, which is fully compliant with the JEDEC GDDR6 (JESD250) standard, supporting up to 16Gbps per pin. The GDDR6 interface supports 2 channels, each with 16bits for a total data width of 32bits. With speed up to 16Gbps per pin, the Innosilicon GDDR6 PHY offers a maximum bandwidth of up to 64GB/s. And, the Innosilicon GDDR6X PHY uses four-level pulse amplitude modulation (PAM4) signaling to extract more efficiency and higher data rates, which will be available in advanced FinFET nodes for leading-edge customer integration.

The Innosilicon system-aware design methodology used for IP Cores delivers a customer focused experience with improved time-to-market and first-time-right quality. Innosilicon offers flexible delivery of IP cores and will work directly with customers to provide a full system signal and power integrity analysis to create an optimized chip layout. In the end, the customer will receive a hard macro solution with a full suite of test software for quick turn-on, characterization and debug.


  • Data rate up to 21Gbps for GDDR6X, 16Gbps for GDDR6
  • PAM4 (only for GDDR6X) and POD-135 compatible signaling
  • Supports both quad data rate (QDR) and double data rate (DDR) data (WCK) mode
  • Driver strength and on-die termination (ODT) auto calibration
  • Supports both Write and Read CRC
  • Per-bit TX and RX data phase adjustment
  • Internal high-performance low-jitter PLL
  • Supports both hardware and software training including WCK2CK training, command training, read training and write training
  • Dynamic eye-diagram training for Write and Read operation
  • TX de-emphasis EQ and RX DFE EQ to improve signal integrity
  • Internal VREF with DFE for data inputs, with receiver characteristics programmable per pin
  • Data bus inversion (DBI) and CA bus inversion (CABI)
  • Supports EDC full rate and half rate hold pattern, programmable EDC tracking bandwidth
  • Various low power modes


  • World’s first silicon-proven commercial GDDR6/6X IP
  • Available in advanced FinFET process nodes
  • JEDEC JESD250 standard compliant (GDDR6)
  • Offers leading performance, power, and area per terabit
  • Optional PI/SI and thermal co-design service
  • Full support from IP delivery to production


GPU GDDR6/6X PHY and Controllers


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