Innosilicon 32G SERDES PHY is a highly configurable PHY supporting speeds up to 32Gbps within a single lane. The 32G Serdes is compatible with PCIe 5/4/3 and next generation PCIe standard protocols, as well as various serial interface protocols (Rapid IO/XAUI/SATA/fiber channel/10G Ethernet etc.).

The 32Gbps SERDES PHY is a low-power, area-optimized silicon IP core designed to meet the power efficiency and performance requirements of applications for next-generation, high-speed wireline and wireless 5G infrastructure, artificial intelligence (AI), data center, edge, and graphics.

Architected to address growing performance/power trade-off challenges, the multi-protocol PHYs allow designers to easily integrate multiple protocols and electrical specifications. The PHY itself can be configured to support a wide range of HS SERDES protocols through the PCS layer and register settings.


  • Supports 32Gbps serial data transmission rate
  • Utilizes 8-bit, 16-bit or 32- bit parallel interface to transmit and receive data
  • Allows integration of high speed components into a single functional block as seen by the device designer.
  • Data and clock recovery from serial stream on the bus
  • Holding registers to stage transmit and receive data
  • Supports direct disparity control for use in transmitting compliance pattern
  • Scramble and descramble with error indication
  • Receiver detection
  • Selectable Tx Margining, Tx De-emphasis and signal swing values
  • All IP related I/O pass 2KV HBM, 100V MM ESD test, 500V CDM
  • Latch-up Targets: +/-200mA @ 125°c, 1.5*Max Vsupply

List of Supported Standards:

Standard Data Rate(s) (Gbps)
HMC-32G-VSR 12.5, 15, 25, 28, 30,32
100G (KR-4) LR/MR/SR 28
100GbE 25.78
USB3.1 10

Test Eye-diagram & Jitter Histogram (32Gbps):


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